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d1912nkpc 20121101-s00003 no.a2154-1/18 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 LV8139JA overview the LV8139JA is a pwm system pre driver ic designed for three-phase brushless motors. this ic reduces motor driving noise by using a high-efficiency, sine wave pwm drive type. it incorporates a full complement of protection circuits and, by combining it with a hybrid ic in the stk611 or stk5c4 series, the number of components used can be reduced and a high level of reliability can be achieved. furthermore, its power-saving mode enables the power consumption in the standby mode to be reduced to zero. this ic is optimally suited for driving various large-size motors such as t hose used in air conditioners and hot-water heaters. features ? three-phase bipolar drive ? sine wave pwm drive ? drive phase setting function (set 0-58 degrees 32 steps: there is an adjustment function corresponding to the ctl pin input) ? supports power saving mode(power saving mode at ctl pin voltage of 0.95v (typ) or less; i cc = 0ma, hb pin turned off) ? supports bootstrap ? automatic recovery type constraint protection circuit ? forward/reverse switching circuit, hall bias pin ? current limiter circuit, low-voltage protection circuit, and thermal shutdown protection circuit ? fg1 and fg3 output (360-degree electrical angle/1 pulse and 3 pulses) bi-cmos ic for brushless motor drive sine wave pwm drive, pre driver ic orderin g numbe r : ena2154
LV8139JA no.a2154-2/18 specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc max v cc pin 18 v output current i o max 15 ma pd max1 independent ic 0.45 w allowable power dissipation pd max2 mounted on a specified circuit board.* 1.05 w ctl pin applied voltage v ctl max 18 v fg1,fg3 pin applied voltage v fg 1 max v fg 3 max 18 v junction temperature tj max 150 c operating temperature topr -40 to +105 c storage temperature tstg -55 to +150 c * specified circuit board : 114.3mm 76.1mm 1.6mm, glass epoxy note 1) absolute maximum ratings represent the va lues that cannot be exc eeded for any length of time. note 2) even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high t emperature, high current, high voltage, or drastic temperature change, the reliability of the ic may be degraded. please contact us for further details. allowable operating range at ta = 25 c parameter symbol conditions ratings unit supply voltage range v cc 9.5 to 16.5 v vreg5 pin output current i reg -10 ma hb pin output current i hb -30 ma fg1,fg3 pin output current i fg 1, i fg 3 10 ma electrical characteristics at ta = 25 c, v cc = 15v ratings parameter symbol conditions min typ max unit supply current 1 i cc 1 4 6 ma supply current 2 i cc 2 at stop (ctl < vil1) 0 10 a output block (pin hin1, hin2, hin3, lin1, lin2 and lin3) high level output voltage v ho i o = -10ma vreg-0.40 vreg-0.25 v upper output on resistance r on h i o = -10ma 25 40 low level output voltage v lo i o = 10ma 0.15 0.25 v lower output on resistance r on l i o = 10ma 15 25 output leakage current i o leak 10 a bootstrap charge pulse wi dth tboot 1.6 2.5 3.4 s output minimum dead time tdt 1.6 2.5 3.4 s 5v constant voltage output (vreg5 pin) output voltage vreg i o = -5ma 4.7 4.9 5.1 v voltage fluctuation v (reg1) v cc = 9.5 to 16.5v, i o = -5ma 100 mv load fluctuation v (reg2) i o = -5 to -10ma 100 mv hall amplifier (pin in1 + , in1 - , in2 + , in2 - , in3 + and in3 - ) input bias current ib (ha) -1 0 a common-mode input voltage range 1 vicm1 w hen a hall element is used 0.3 vreg-1.8 v common-mode input voltage range 2 vic m2 single-sided input bias mode (when a hall ic is used) 0 vreg v hall input sensitivity vhin sine wave, hall element offset = 0v 80 mvp-p hysteresis width v in (ha) 15 30 45 mv input voltage low ? high vslh 5 15 25 mv input voltage high ? low vshl -25 -15 -5 mv continued on next page. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV8139JA no.a2154-3/18 continued from preceding page. ratings parameter symbol conditions min typ max unit csd oscillator circuit (csd pin) high level output voltage v oh (csd) 2.75 2.95 3.15 v low level output voltage v ol (csd) 0.85 1.05 1.25 v amplitude v (csd) 1.7 1.9 2.1 vp-p external capacitor charging current ichg1 (csd) vchg1 = 2.0v -14 -10 -6 a external capacitor discharging current ichg2 (csd) vchg2 = 2.0v 6 10 14 a lock detection on/off time ratio lrto drive off/drive on 11 pwm oscillator (pwm pin) high level output voltage v oh (pwm) 3.3 3.5 3.7 v low level output voltage v ol (pwm) 1.3 1.5 1.7 v amplitude v (pwm) 1.8 2.0 2.2 vp-p oscillation frequency f (pwm) c = 2200pf, r = 15k (design target value) 17.3 khz current limiter operation (rf pin) limiter voltage vrf 0.225 0.25 0.275 v thermal shutdown protection operation thermal shutdown protection operating temperature tsd * design target value (junction temperature) 150 175 c hysteresis width tsd * design target value (junction temperature) 35 c th pin protection start voltage vth 0.50 0.65 0.80 v hysteresis width vth 0.32 0.42 0.52 v hb pin output on resistance r on (hb) ihb = -10ma 10 20 output leakage current i l (hb) power saving mode v cc = 15v 10 a low voltage protection circuit (detecting v cc voltage) operation voltage vsd 7.4 7.9 8.4 v hysteresis width vsd 0.35 0.5 0.65 v fg1 fg3 pin output on resistance r on (fg) ifg = 5ma 40 60 output leakage current i l (fg) vfg = 18v 10 a ctl amplifier (drive mode) input voltage range v in (ctl) 0 v cc v high level input voltage v ih (ctl) hin pin pwm on duty 100% 4.4 4.6 4.8 v middle level input voltage 1 (at drive start) v im 1 (ctli) hin pin pwm on duty 0% 2.15 2.35 2.55 v middle level input voltage 2 (during drive) v im 2 (ctli) hin pin pwm on duty 0% 1.9 2.1 2.3 v input current (during drive in 120-degree current-carrying mode) i ih 1 (ctli) vctl = 3.5v 13 25 37 a input current (during drive in sine wave current-carrying mode) i ih 2 (ctli) vctl = 3.5v 10 20 30 a ctl amplifier (power saving mode) low level input voltage v il 1 (ctl) power saving mode 0.75 0.95 1.15 v hysteresis width ctl 0.15 0.35 0.55 v continued on next page.
LV8139JA no.a2154-4/18 continued from preceding page. ratings parameter symbol conditions min typ max unit f/r pin high level input voltage range v ih (fr) 3.0 vreg v low level input voltage range v il (fr) 0 0.7 v input open voltage v io (fr) 0 0.3 v hysteresis width v is (fr) 0.15 0.3 0.45 v high level input current i ih (fr) vf/r = vreg 25 45 65 a low level input current i il (fr) vf/r = 0v -2 0 +2 a fault pin drive stop voltage vfof 0 0.5 v drive start voltage vfon 3.0 vreg v input open voltage v io (flt) 4.6 vreg v high level input current i ih (flt) vfault=vreg 0 10 a low level input current i il (flt) vfault=0v -200 -160 -120 a adp1 pin (drive phase adjustment) minimum lead angle vadp01 vadp1 = 0v 0 2 deg maximum lead angle vadp16 vadp1 = vreg 56 58 deg current ratio with the adp2 pin current adp vctl = 5.5v, iadp1/iadp2 1.8 2 2.2 a/a adp2 pin (drive phase adjustment) high level output voltage vadp2h vctl = 5.5v 2.25 2.45 2.65 v low level output voltage vadp2l vctl = 1.5v 0 0.3 v dpl pin (drive-phase-adjustment limit setting pin) lead angle limit high level voltage vdplh 3.3 3.5 3.7 v lead angle limit low level voltage vdpll 1.3 1.5 1.7 v * these are design target values and no measurements are made.
LV8139JA no.a2154-5/18 package dimensions nit : mm (typ) 3191c pin assignment 0 0.38 0.16 0.5 1.0 1.5 --40 --20 100 40 60 20 80 0 120 ambient temperature, ta -- c allowable power dissipation, pd max -- w pd max - ta specified circuit board : 114.3 76.1 1.6mm 3 glass epoxy independent ic mounted on a specified circuit board. 1.05 0.45 sanyo : ssop30(275mil) 9.75 5.6 7.6 0.22 0.65 (0.33) 1 30 0.5 0.15 1.5 max 0.1 (1.3) 30 1 in1 + hb 29 2 in1 - hin1 28 3 in2 + hin2 27 4 in2 - hin3 26 5 in3 + lin1 25 6 in3 - lin2 24 7 gnd lin3 23 8 v cc fault 22 9 ctl th 21 10 dpl rf 20 11 fg3 tgnd 19 12 fg1 vreg5 18 13 adp2 fr 17 14 csd rpwm 16 15 adp1 cpwm LV8139JA top view
LV8139JA no.a2154-6/18 sample application circ uit 1 (hall ic, hic) the hall ic to be used must be of open-collector or open-drain output type, and it must be pulled up by vreg5. the type of hall ic incorporating a pull-up resistor cannot be used. furthermore, when using an element that cannot turn off the control power while vm is being applied, the control power must be supplied from the v cc pin rather than from the hb pin. + control circuit stk5c4-xxx pwm osc rotate detect drive phase setting drive phase revise curr lim pre driver csd osc ctl amp fr ctl ctl input f/r input fr rpwm cpwm tsd hb hb fg mosc lvsd vreg vreg5 v cc v cc in3 - in3 + hall hys amp hall ic open corrector/drain type reset v cc gnd out v cc gnd out v cc gnd out + v cc vb1 vs1,uout vs2,vout vs3,wout vb2 vb3 v dd v ss m vm in2 - in2 + in1 - in1 + vreg5 csd dpl adp2 adp1 fg1 fg3 vreg5 fg3 output fault fault fault enable hin1 hin1 hin2 hin2 hin3 hin3 lin1 lin1 lin2 lin2 lin3 vreg5 1k 1k 1k 68 22 vreg5 lin3 rf th rf u - ,v - ,w - rcin th2 itrip th1 vs1,uout vs2,vout vs3,wout gnd tgnd fg1 output pwm generate
LV8139JA no.a2154-7/18 sample application circuit 2 (hall ic, fet) the hall ic to be used must be of open-collector or open-drain output type, and it must be pulled up by vreg5. the type of hall ic incorporating a pull-up resistor cannot be used. furthermore, when using a gate driver that cannot turn off the control power while vm is being applied, the control power must be supplied from the v cc pin rather than from the hb pin. an element with a short reverse recovery time must be selected as the output fet. + control circuit pwm osc rotate detect drive phase setting drive phase revise curr lim pre driver csd osc ctl amp fr ctl ctl input f/r input fr rpwm cpwm tsd hb hb 22 fg mosc lvsd vreg vreg5 v cc v cc in3 - in3 + hall hys amp hall ic open corrector/drain type reset in2 - in2 + in1 - in1 + vreg5 csd dpl adp2 adp1 fg1 fg3 vreg5 fg3 output fault hin1 hin2 hin3 lin1 lin2 lin3 vreg5 rf rf th gnd tgnd fg1 output vreg5 68 mura260t3 mura260t3 mura260t3 + m vm vout uout wout 1k 1k 1k v cc gnd out v cc gnd out v cc gnd out ncp5106 vboot v cc 1 8 hout in_hi 2 7 bridge in_lo 3 6 drv_lo gnd 4 5 ncp5106 vboot v cc 1 8 hout in_hi 2 7 bridge in_lo 3 6 drv_lo gnd 4 5 ncp5106 vboot v cc 1 8 hout in_hi 2 7 bridge in_lo 3 6 drv_lo gnd 4 5 pwm generate
LV8139JA no.a2154-8/18 pin functions pin no. pin name pin function equivalent circuit 1 2 3 4 5 6 in1 + in1 - in2 + in2 - in3 + in3 - hall signal input pins. the high state is when in + is greater than in - , and the low state is the reverse. an amplitude of at least 100mvp-p (differential) is desirable for the hall signal inputs. if noise on the hall signals is a problem, insert capacitors between in + and in - pins. if input is provided from a hall ic, fix one side of the inputs (either the ?+? or ?-? side) at a voltage within the common-mode input range (0.3v to vreg-1.8v), and use the other input side as an input over the 0v to vreg range. vreg 1 5 3 2 6 4 500 500 7 gnd ground pin of the control circuit block. 8 v cc power supply pin for control. insert a capacitor between this pin and ground to prevent the influence of noise, etc. 9 ctl control input pin. when ctl pin voltage rises, the ic changes the output signal pwm duty to increase the torque output. in sine wave mode, nch fet (in equivalent circuit diagram) off in 120-degree current-carrying mode, nch fet on 9 45k vreg v cc 86.6k 38.4k 10 dpl setting pin for drive phase adjustment limit. this pin is used to limit the lead angle of the drive phase. the lead angle is limited to zero degrees when the voltage is 1.5v or lower and the limit is released when the voltage is 3.5v or higher. 10 500 vreg 11 12 fg3 fg1 fg3 : 3-hall fg signal output pin. 8-pole motor outputs 12 fg pulses per one rotation. in power saving mode, high-level is output. fg1 :1-hall fg signal output pin. 8-pole motor outputs 4 pulses per one rotation. in power saving mode, high-level is output. vreg 11 12 25 continued on next page.
LV8139JA no.a2154-9/18 continued from preceding page. pin no. pin name pin function equivalent circuit 13 adp2 setting pin for phase drive correction. this pin sets the amount of correction made to the lead angle according to the ctl input. insert a resistor between this pin and ground to adjust the amount of correction. 500 500 13 vreg vreg v cc 14 csd pin to set the operating time of the motor constraint protection circuit. insert a capacitor between this pin and ground. connect this pin to ground when the constraint protection circuit is not going to be used. 500 500 v reg 14 15 adp1 drive phase adjustment pin. the drive phase can be advanced from 0 to 58 degrees during 180-degree current carrying drive. the lead angle becomes 0 degrees when 0v is input and 58 degrees when vreg is input. v cc 500 500 vreg ad 15 16 cpwm triangle wave oscillation pin for pwm generation. insert a capacitor between this pin and ground and a resistor between this pin and rpwm for triangle wave oscillation. 200 vreg 16 17 rpwm oscillation pin for pwm generation. insert a resistor between this pin and cpwm. vreg 17 continued on next page.
LV8139JA no.a2154-10/18 continued from preceding page. pin no. pin name pin function equivalent circuit 18 20 fr tgnd fr forward/reverse rotation setting pin. a low-level specifies forward rotation and a high-level specifies reverse rotation. this pin is held low when open. tgnd test pin. connect this pin to ground. 2k 100k vreg 18 20 19 vreg5 5v regulator output pin (control circuit power supply). insert a capacitor between this pin and ground for power stabilization. 0.1 f or so is desirable. v cc 50 19 21 rf output current detection pin. this pin is used to detect the voltage across the current detection resistor (rf). the maximum output current is determined by the equation i out = 0.25v/rf. vreg 21 5k 22 th thermistor connection pin. the thermistor detects heat generated from hic and turns off the drive output when an overheat condition occurs. all the hin/lin output pins are set to low at a pin voltage of 0.6v or less. * for further details, refer to ?description of LV8139JA.? 500 22 vreg continued on next page.
LV8139JA no.a2154-11/18 continued from preceding page. pin no. pin name pin function equivalent circuit 23 fault hic protection signal input pin. this pin accepts an error mode detection signal generated by the hic side. with a low-level input, the error mode detection condition is established, and all the hin/lin output pins are set to low. * for further details, refer to ?description of LV8139JA.? 500 30k 23 vreg 24 25 26 27 28 29 lin3 lin2 lin1 hin3 hin2 hin1 lin1, lin2, and lin3 : l side drive signal output pin. generate 0 to vreg push-pull outputs. hin1, hin2, and hin3 : h side drive signal output pin. generate 0 to vreg push-pull outputs. 500 vreg 24 27 25 28 26 29 30 hb hall bias hic power supply pin. insert a capacitor between this pin and ground. this pin is set to high-impedance state in power saving mode. by supplying hall bias and hic power using this pin, the power consumption by hall bias and hic in power saving mode can be reduced to zero. v cc 30
LV8139JA no.a2154-12/18 timing chart (in = ? h ? indicates the state in which in + is greater than in - .) (1) f/r pin = l normal hall input lead angle=0 in1+ in1- in2+ in1- in3+ in1- u hin1 on on off off on on off off on on off off lin1 hin2 lin2 hin3 lin3 max duty 0% v w u hin1 on on off off on on off off on on off off lin1 hin2 lin2 hin3 lin3 v w 3 hall fg 1 hall fg uout h duty max duty 0% vout h duty max duty 0% wout h duty in1 in2 in3 h l h h l l l h l l h h l l h h l h h l l h h l h h l l h l l h h l l h pwm f/r="l" 120 energization f/r="h" 120 energization in reverse rotate f/r="l" sin wave drive method pwm pwm pwm pwm pwm pwm pwm pwm pwm pwm pwm pwm the energization is switched to 120 wher 3 hall fg frequency is 5.15hz (typ) or lower a direction of rotation is detected from hall signal according to f/r pin input if the motor rotates in reverse against f/r pin input 120 energization is maintained forcibly
LV8139JA no.a2154-13/18 (2) f/r pin = h reverse hall input lead angle=0 in1+ in1- in2+ in1- in3+ in1- u hin1 on on off off on on off off on on off off lin1 hin2 lin2 hin3 lin3 max duty 0% v w u hin1 on on off off on on off off on on off off lin1 hin2 lin2 hin3 lin3 v w 3 hall fg 1 hall fg uout h duty max duty 0% vout h duty max duty 0% wout h duty in1 in2 in3 l l h l h h h h l h l l h l h l l h l h h l h l h h l l h l h l l h l h pwm pwm pwm pwm pwm pwm pwm pwm f/r="h" 120 energization f/r="h" sin wave drive method f/r="l" 120 energization in reverse rotate pwm pwm pwm pwm the energization is switched to 120 wher 3 hall fg frequency is 5.15hz (typ) or lower a direction of rotation is detected from hall signal according to f/r pin input if the motor rotates in reverse against f/r pin input 120 energization is maintained forcibly
LV8139JA no.a2154-14/18 functional description ? basic operation of 120-degree ? sine wave current-carrying switching at startup, this ic starts at 120-degr ee current-carrying. the current-carrying is switched to sine wave when the 3-hall fg frequency is 5.15hz (typ) or above and the rising edge of the in2 signal has been detected twice in succession. concerning the hall si gnal input sequence this ic controls the motor rotation direction commands and hall signal input sequence in order to set the lead angle. if the motor rotation direction commands and hall signal input sequence do not conform to what is shown on the timing chart, the motor is driven by 120- degree current-carrying. shown below are two hall signal input sequences. sequence 1 : when the hall signal has been input with the following logic in1 h h h l l l in2 l l h h h l in3 h l l l h h when f/r pin input is high 120-degree current-carrying when f/r pin input is low 180-degree current-carrying sequence 2 : when the hall signal has been input with the following logic in1 h l l l h h in2 l l h h h l in3 h h h l l l when f/r pin input is high 180-degree current-carrying when f/r pin input is low 120-degree current-carrying ? ctl pin input a) power-saving mode v ctl < v il (0.95v : typ) ? l in 1 to l in 3 and h in 1 to h in 3 outputs all set to low ? i cc = 0, hb pin = off the power consumption of the ic can now be set to 0, and the power consumption of the hall element connected to the hb pin and the output block can also be set to 0. b) standby mode while stopped: v il < v ctl < v im 1 (2.33v: typ); while running: v il < v ctl < v im 2 (2.1v: typ) the u in 1 to 3 outputs are set to low, and the bootstrap charge pulse (pulse width: 2.5 s: design target) is output to the l in 1 to 3 outputs in preparation for drive start. c) drive mode at drive start: v im 1 < v ctl < 7v; during drive: v im 2 < v ctl < 7v (v ih 4.7v: typ) the motor is driven at the pwm duty ratio that corresponds to v ctl . when v ctl is increased, the pwm duty ratio increases, and the maximum duty ratio is established at ?v ih .? d) test mode 8.5v < v ctl < v cc when the ctl pin voltage is 8v or higher, the ic enters the test mode, and the motor is driven at the 120-degree current-carrying and maximum duty* ratio. * when the pwm oscillation frequency setting is 17khz, th e maximum duty ratio in the 120-degree current carrying mode is 88% (typ). ? the ctl pin is pulled down by 170k (120-degree mode) : typ, 131.6k (sine wave mode) : typ inside the ic. caution is required when the control input voltage input is subjected to resistance division, for example. ? bootstrap capacitor initial charging mode when the mode is switched from the power-saving mode to th e standby mode and then to the drive mode, the ic enters the bootstrap capacitor charging mode (h in 1, h in 2, h in 3 pins = l l in 1, l in 2, l in 3 pins = h 4.55ms typ) in order to charge the bootstrap capacitor.
LV8139JA no.a2154-15/18 ? drive phase adjustment during 180-degree current-carrying drive, any lead angle from 0 to 58 degrees can be set using the adp1 pin voltage (lead angle control). this setting can be adjusted in 32 steps (in 1.875-degree increments) from 0 to 58 degrees using the adp1 pin voltage, and it is updated every hall signal cycle (it is sampled at the rising edge of the in3 input and updated at its falling edge). a number of lead angle adjustments proportionate to the ctl pin voltage can be undertaken by adjusting the resistance levels of resistors connected to the adp1 pin, adp2 pin and dpl pin. when these pins are not going to be used, reference must be made to section 4.5, and the pins must not be used in the open status. furthermore, a resistance of 47k or more must be used for the resistor (r adp2) that is connected to the adp2 pin. 1. the slopes of v ctl and vadp1 can be adjusted by setting the resistance level of the resistor (radp1) connected to adp1 (pin 15). 2. the adp2 pin rise can be halted (a limit on the lead angle adjustment can be set by means of the ctl voltage) by setting dpl (pin 10). 3. the offset and slope can be adjusted as desired by settin g radp1 and radp12 of adp1 (pin 15). (it is also possible to set a limit on the lead angle adjustment by means of the ctl voltage by setting dpl.) 4. when the lead angle is not adjusted adp1 pin: shorted to ground; adp2 pin and dpl pin: pulled down to ground using the resistors 5. when the lead angle is not adjust ed by means of the ctl pin voltage (for use with a fixed lead angle) adp1 pin: lead angle setting by resistance division from vreg5; adp2 pin and dpl pin: pulled down to ground by the resistors vadp2=(vctl-vim2)(2.5/(vih-vim2)) =(vctl-2.1v)(2.5/(4.6v-2.1v)) iadp2=vadp2/radp2 iadp1=iadpriadp2 vadp1=iadp1radp1 vreg5 rdpl1 33k 47k iadp2 iadp1 radp2 radp1 dpl adp2 adp1 vih(typ:4.6v) vim2(typ:2.1v) adp1(radp1=47k ) adp1(radp1=22k ) vctl[v] 2.34v vreg 0v adp2 vadp2h vadp1, vadp2[v] 58 0 lead angle[] 32 steps vadp2=(vctl-vim2)(2.5/(vih-vim2)) iadp2=vadp2/radp2 iadp1=iadpriadp2 vadp1=iadp1radp1 dpllim=vdpl1.36 vreg5 rdpl1 iadp2 iadp1 radp2 radp1 dpl adp2 adp1 rdpl2 vctl[v] 2.46v vreg 0v adp2 vadp1, vadp2[v] 1.23v 1.17v adp1(radp1=47k ) adp1(radp1=22k ) 3.33v dpllim 58 0 lead angle[] 32 steps vih(typ:4.6v) vim2(typ:2.1v) 33k 33k 47k vreg5 rdpl1 vreg5 radp12 vadp2=(vctl-vim2)(2.5/(vih-vim2)) iadp2=vadp2/radp2 iadp1=iadpriadp2 vadp1=((radp1radp12)/(radp1+radp12))iadp1 +(radp1/(radp1+radp12))vreg iadp2 iadp1 radp2 radp1 dpl adp2 adp1 vctl[v] vadp2h vreg 0v adp2 vadp1, vadp2[v] 0.86v adp1 (radp1=47k ,radp12=220k ) adp1 (radp1=33k ,radp1=33k ) 4.17v 58 0 lead angle[] 32 steps vih(typ:4.6v) vim2(typ:2.1v) 33k 47k
LV8139JA no.a2154-16/18 description of lv8139 1. current limiter circuit the current limiter circuit limits the output current peak value to a level determined by the equation i = v rf /rf (where v rf = 0.25v typ, rf is the value of th e current detection resistor). the current limiter operates by reducing the h in output on duty to suppress the current. the current limiter circuit detects the reve rse recovery current of the diode due to pwm operation. to assure that the current limiting function does not malfunction, its operation has a delay of approx. 1 s. if the motor coils resistance or a low inductance, current fluctuation at startup (when there is no back electromotive force in the motor) will be rapid. the delay in this circuit means that at such times the current limiter circuit may operate at a point well above the set current. application must take this increase in the current due to the delay into account when the current limiter value is set. 2. power saving circuit (ctl pin) this ic goes into the power saving mode that stops operatio n of all the circuits to reduce the power consumption. if the hb pin is used for the hall element bias and the output block, the current consumption in the power-saving mode is zero. 3. hall input signal signals with an amplitude in excess of the hysteresis is re quired for the hall inputs. however, considering the influence of noise and phase displacement, an am plitude of over 100mv is desirable. if noise disrupts the output waveform, this must be prevente d by inserting capacitors or other devices across the hall inputs. the hall inputs are used by the circuit inside the ic as decision signals so if noise enters, a malfunction occurs in the operation. although the circuit is designed to tolerate a certain amount of noise, care is required. furthermore, when the hall signal amplitude has changed as a result of a change in temp erature, the drive phase may possibly shift due to the hall amplifier hysteresis. it is the us er who is responsible for giving due consideration to this aspect. use of a hall ic is recommended un less there is a reason not to use one. if all three phases of the hall input signal go to the same input state (hhh or lll), all the hin/lin outputs are set to low. if the outputs from a hall ic are used, fix one side of the inputs (either the ?+? or ? ? ? side) at a voltage within the common-mode input voltage range (0.3v to vreg?1.8v), and use the other input side as an input over the 0v to vreg range. 4. constraint protection circuit a constraint protection circuit is incorporated in order to protect the output elements and motor when the motor is constrained. the circuit is activ ated when the hall signal is not switched fo r a specific period of time when the motor is in operation. the counter is reset each time the motor rotates 360 degrees in terms of the electrical angle. all the h in and l in outputs are set to the low level when the constraint protection circuit is in operation. this time is determined by the capacitance of the capacitor connect ed to the csd pin. oscillation time of csd pin (1 pulse) t = | (v oh -v ol )/ichg1 | c ( f) + | (v oh -v ol )/ichg2 | c ( f) constraint protection detection time t1 (s) = t 256 (count) constraint protection time t2 (s) = t 2816 (count) when a 0.022 f capacitor is attached, t = 8.36ms, t1 = 2.14s and t2 = 23.54s are established as the typical ratings. after the motor has been constrained, the constraint protection state is established at 2.14 (s), and then after 23.54 (s) has elapsed, the constraint protection circuit is reset automati cally. a time that provides so me leeway in the motor start time that factors in any fluctuations must be selected as the setting. conditions for releasing the constraint protection state other than by automatic resetting: when ctl pin voltage < v im 2 input protection release and csd count reset when the low level is detected on the th pin protection release and csd count reset when fr has been switched protection release and csd count reset when tsd protection is detected csd count stop
LV8139JA no.a2154-17/18 5. power supply stabilization since this ic adopts a switching drive technique, the power -supply line level can be disrupted easily. thus capacitors large enough to stabilize the power supply voltage must be inserted between the v cc pins and ground. if the electrolytic capacitors cannot be connected close to thei r corresponding pins, ceramic capacitors of about 0.1 f must be connected near these pins. if diodes are inserted in the power-supply line to prevent de struction of the device when th e power supply is connected with reverse polarity, the power supply lin e levels will be even more easily disrupted, and even larger capacitors must be used. 6. vreg stabilization connect a capacitor with a capacitance of 0.1 f or more between vreg5 and ground in order to stabilize the vreg voltage that is the power supply of the control circuit. the ground lead of that capacitor must be located as close as possible to the control system ground (sgnd) of the ic. 7. forward/reverse switching (f/r pin) switching between forward rotation and reverse rotation must not be undertaken while the motor is running. 8. th pin the th pin must normally be pulled up to vreg5 for use. when this pin has been set to low, all the h in /l in outputs are set to low. when reset is initiated, the bootstrap initial charging mode is established. 9. fault pin the fault pin must normally be pulled up to vreg5 for use. when this pin has been set to low, all the h in /l in outputs are set to low. when reset is initiated, th e bootstrap initial charging mode is established. all the outputs are set to low. in addition, the fg1/fg3 output goes off, too. when reset is initiated, the bootstrap initial charging mode is established. 10. pwm frequency setting fcpwm 1/ (1.7cr) components with good temperature characteristics must be used. an oscillation frequency of about 17khz is obtained when a 2200pf capacitor and 15k resistor are used. if the pwm frequency is too low, switching noise will be heard from the motor; conversely, if it is too high, the output power loss will increase. for this reason, a frequency between 15khz and 30khz or so is desirable. the capacitor ground must be connected as close as possible to the cont rol system ground (sgnd pin) of the ic to minimize the effect s of the outputs. if there are no fluctuations in the capac itance or resistance of the external ca pacitors or resistors and only the ic fluctuations are to be considered, an actual capability of 3% can be expected. 11.concerning the power-raising operation this ic provides sine wave pwm drive so it performs operations similar to synchronous rectification. these operations are such that current is sometimes returned to the motor power supply side depending on the conditions of use. for instance, this may happen when: ? the drive phase is shifted. ? the motor has been suddenly accelerated. ? the output duty ratio has been decreased sharply while the motor is running. if the output duty ratio has been decreased sharply, it is high ly likely that current will return to the motor power supply. the extent to which the motor supply voltage increases diffe rs depending on the size of the capacitors used in the product that incorporates the motor, th e size of the capacitor inserted between the motor power supply and ground on the motor circuit board and the motor used; as such, it is the us er who is responsible for giving due consideration to this aspect. it is necessary to take remedial action such as increasing the capacitance of the capacitors or reducing the speed at which the duty ratio will be reduced when the motor supply voltage rises to ensure that the maximum withstand voltage of the element used for output is not exceeded.
LV8139JA ps no.a2154-18/18 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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